The present invention relates to a semiconductor device, particularly to a technology effective when applied to a semiconductor device using SOI (silicon on insulator) substrate.
As a semiconductor device capable of suppressing generation of parasitic capacitance, semiconductor devices having, for example, an SOI substrate are used currently. The SOI substrate is a semiconductor substrate having a BOX (buried oxide) film (embedded oxide film) formed over a support substrate made of, for example, high-resistance Si (silicon) and, on the BOX film, a thin layer (silicon layer) composed mainly of Si (silicon). Generation of parasitic capacitance in a diffusion region formed in the silicon layer can be reduced by forming an MOSFET (metal oxide semiconductor field effect transistor) over the SOI substrate. A semiconductor device manufactured using the SOI substrate is therefore expected to have an improved integration density and an improved operation speed and be latchup free.
Patent Document 1 (Japanese Patent Laid-Open No. 2007-288554) discloses, in a switched capacitor circuit formed over an SOI substrate and having a differential structure, a technology of reducing a leakage current, upon switch off, of a transistor used for a switch to be coupled at one end thereof to an analog ground which is at an intermediate potential between Vss and Vdd. According to the technology disclosed in Patent Document 1, it is possible to realize a source-tie transistor having a potential of a channel region fixed using a coupling member formed outside agate end portion.
Patent Document 2 (Japanese Patent Laid-Open No. 2003-318405) discloses, in a device using an SOI substrate, a technology of forming a body (well) contact portion in the vicinity of the end portion of a gate electrode in a gate electrode width direction to fix the potential of a channel region and thereby realizing a high-speed and stable operation.
Patent Document 3 (Japanese Patent Laid-Open No. 2007-287718) discloses, in a semiconductor device using an SOI substrate, a technology of fixing the potential of a body region formed in a silicon layer over a BOX film with a view to reducing the parasitic capacitance of an MOSFET formed over the SOI substrate. According to this technology, a semiconductor region (heavily-doped region) of a first conductivity type is formed by introducing an impurity of the first conductivity type at a high concentration into a continuous region from a portion of the first conductivity type body (well) region below a gate electrode extending over the SOI substrate along the main surface of the SOI substrate to a portion of source and drain regions of a second conductivity type formed in the silicon layer to sandwich therebetween the body region in a gate length direction. This means that the body region and the source region formed in the silicon layer below a gate electrode of an MOSFET having the gate electrode and source and drain regions are electrically coupled to each other via the low-resistance heavily-doped region of the first conductivity type. In addition, the potential of the body region is also controlled in the vicinity of the end portion of the gate electrode in the gate width direction. A portion of this heavily-doped region is formed in a portion of the source region in the plane of the SOI substrate and the other portion of the source region having no heavily-doped region therein configures the MOSFET together with the drain region and the gate electrode. According to the technology disclosed in Patent Document 3, the potential of the body region can be fixed via the heavily-doped region and a region in the vicinity of the end portion of the gate electrode. Incidentally, the source region and the body region are electrically coupled to each other via a silicide layer formed over the heavily-doped region and the source region so that they have the same potential.
Patent Document 4 (Japanese Patent Laid-Open No. 2007-287747) discloses, in a semiconductor device using an SOI substrate, a technology of fixing the potential of a body region formed in a silicon layer over a BOX film with a view to reducing the parasitic capacitance of an MOSFET formed over the SOI substrate. According to this technology, the potential of the body region is fixed via a semiconductor region of a first conductivity type formed in the vicinity of the end portion of a gate electrode in the gate width direction of the MOSFET and electrically coupled to a body (well) region of the first conductivity type. This document also discloses a technology of forming a coupling region of the first conductivity type continuously from a portion of a second conductivity type source region of the MOSFET to the body region and fixing the potential of the body region via the coupling region and the source region. Incidentally, the source region and the body region are electrically coupled to each other via a silicide layer formed over the coupling region and the source region so that they have the same potential.
Patent Document 5 (Japanese Patent Laid-Open No. 2008-172262) discloses, in a semiconductor device using an SOI substrate, a technology of fixing the potential of a body region formed in a silicon layer over a BOX film with a view to reducing the parasitic capacitance in an MOSFET formed over the SOI substrate. According to this technology, the potential of the body region is fixed via a low-resistance semiconductor region of a first conductivity type formed in the vicinity of an end portion of a gate electrode in a gate width direction of the MOSFET and electrically coupled to a body (well) region of the first conductivity type. This document also discloses a technology of forming a coupling region of the first conductivity type continuously from a portion of a second conductivity type source region of the MOSFET to the body region and fixing the potential of the body region via the coupling region and the source region. Incidentally, there is also disclosed a technology of forming a portion of the gate electrode on the top surface of the SOI substrate at the interface of the coupling region and the source region in order to prevent the source region and the body region from having the same potential due to their electrical coupling via a silicide layer formed over the coupling region and the source region.    [Patent Document 1] Japanese Patent Laid-Open No. 2007-288554    [Patent Document 2] Japanese Patent Laid-Open No. 2003-318405    [Patent Document 3] Japanese Patent Laid-Open No. 2007-287718    [Patent Document 4] Japanese Patent Laid-Open No. 2007-287747    [Patent Document 5] Japanese Patent Laid-Open No. 2008-172262